Applications with optoelectronic components are increasingly gaining in importance. These include not only simple luminous means such as lamps but also backlighting systems, for example for LCD screens or monitors. In this case, the term optoelectronic component denotes an element which emits light in an operation mode when supplied with electrical energy. This includes not only semiconductor-based light-emitting diodes but also organic light-emitting diodes, combinations of organic and inorganic compounds suitable for light emission and other light-emitting components.
In some applications, very high light powers are required, for example for projectors. This primarily involves the use of luminous bodies which emit light in different colors, such that a white mixed color arises.
In order to achieve the highest possible luminances, it is often the case that different optoelectronic components are positioned on a common chip and subsequently driven and supplied with energy by means of corresponding leads. The subdivision into different individual chips has the advantage that, firstly, luminosity and color can be regulated better and, secondly, the probability of failure is reduced and/or the repair possibilities are improved. By contrast, on account of inaccurate positioning, a non-uniform light distribution and luminance can arise, which can become apparent in a disturbing manner.
One object of the invention is to provide a method in which a higher and more uniform luminance can be achieved when producing a luminous means of the type described above.
According to an embodiment of the invention, the luminance and the uniformity, also designated as etendue for simplification, can be improved by means of a suitable structuring of a planar chip mounting region on which the individual luminous bodies are applied.
One configuration involves providing a carrier serving as a heat sink, said carrier comprising a planar chip mounting region. The carrier can have a metal core, a metal substrate having such a planar chip mounting region. A ceramic substrate having a metalized chip mounting region, a PCB (Printed Circuit Board) having a planar, if appropriate metalized, chip mounting region or else a leadframe having such a region can likewise be provided as the carrier. Depending on the respective carrier, the subsequent chip mounting region is pretreated, for example metalized. Any substrate with SMT capability that can be metalized in partial regions in order to form a planar chip mounting region is suitable as the carrier.
The planar chip mounting region is structured for the purpose of producing a first partial region and at least one second partial region. The structuring is effected in such a way that the first partial region has a solder-repellent property after structuring. Alternatively, the first partial region becomes solder-repellent as a result of the structuring of the chip mounting region, such that the chip mounting region is solder-repellent in the first partial region and solder-attracting in the second partial region.
The terms “solder-repellent” or “solder-repellent property” are understood to mean a property of the first partial region which has the effect that, upon subsequent application of a solder or solder flux, the latter does not wet or scarcely wets the first partial region. Consequently, after the application of a solder on the planar chip mounting region, the solder is concentrated primarily in the second partial region and wets the latter.
Afterward, at least one optoelectronic body, preferably an optoelectronic semiconductor component, is applied to the solder in the at least one second partial region and fixedly connected to the carrier. As a result of the structuring and the production of the solder-repellent first partial region, the optoelectronic body applied on the solder is thus fixed in the second partial region. During production in the liquid state of the solder, the optoelectronic body floating on the solder “follows” the solder into the second partial region since the solder wets the chip mounting region only in this partial region.
The structuring of the planar chip mounting region into partial regions having a solder-repellent and solder-attracting or wetting property thus makes it possible to form partial regions in which one or more optoelectronic bodies are fixed and connected to the chip mounting region by means of a previously applied solder.
Afterward, an electrical contact-connection, suitable for feeding electrical energy to the optoelectronic luminous body, can be formed.
In one configuration, it is expedient in this regard for the carrier serving as a heat sink already to be formed as an electrode or for the planar chip mounting region to be formed as an electrode. In this case, the planar chip mounting region serves not only as part of the heat sink, but also as electrical contact to the optoelectronic component.
In one configuration, the planar chip mounting region comprises, in the second partial region, at least one metallic partial layer which is at least partly wettable by the solder. The partial layer can comprise, for example, gold, silver or some other non-oxidizing material. In one embodiment, the planar mounting region comprises different partial layers composed of different metals that are arranged one above another. Said metals can comprise, for example, nickel, copper, aluminum, silver, gold, titanium or tungsten. In this case, a gold layer can be applied above a nickel layer in order to prevent a diffusion of gold into underlying partial layers, for example composed of copper.
One configurational form of the method proposes, for the purpose of structuring the chip mounting region and producing the first partial region, removing parts of the gold layer within the chip mounting region and oxidizing the underlying nickel layer. The oxidation of the underlying layer, in particular of a nickel layer, produces a first partial region having a solder-repellent property, such that the solder applied thereto does not wet this partial region, or wets it only very slightly.
In one configuration, such a structuring is achieved by providing an optical light source, preferably a laser. Afterward, for the purpose of producing the structuring of the planar chip mounting region, the first partial region of the planar chip mounting region is irradiated by means of the optical light source and at least one of the metallic partial layers is thus oxidized. In one exemplary embodiment, as a result of the irradiation, a surface material of the first partial region is melted or evaporated and an underlying material uncovered is oxidized. This underlying oxidized material has the solder-repellent properties. By way of example, the surface material can be gold, aluminum or silver which is evaporated by the irradiation preferably by means of a laser. An underlying material forming a further partial layer is uncovered. Said material can comprise nickel, for example. The uncovered material is then oxidized, for example with the aid of the optical radiation source, but also by means of other physical or chemical methods.
In the case of an uncovered nickel layer, the latter is oxidized by the laser beam and the nickel thus oxidized is solder-repellent.
Generally, for the purpose of producing a material having a solder-repellent property, a surface material of the planar chip mounting region can be chemically altered by physical or chemical methods and form a compound.
In another configuration, the planar chip mounting region is structured by a soldering resist layer being applied on the planar chip mounting region. Said solder resist layer is likewise solder-repellent. Afterward, the soldering resist layer is structured for the purpose of producing the first and second partial regions and is then removed in the second partial region, such that the underlying surface of the second partial region of the chip mounting region is uncovered again. The soldering resist layer can be structured for example by means of suitable mask methods and exposure. The rest of the soldering resist layer remains on the chip mounting region to form the first partial region.
In a further configuration, a soldering resist layer is directly selectively applied to the planar chip mounting region and the first partial region is thus defined. In this case, too, the soldering resist layer is solder-repellent. Such application can be effected by means of a stencil method or a solder dispensing method, for example. If necessary, by uncovering and/or processing sections of the second partial region, these can subsequently be cleaned of an undesirably applied soldering resist layer, such that the second partial region again comprises the surface that is wettable by solder.
A solder dispensing method is appropriate for applying a solder to the planar chip mounting region within the second partial region. This is advantageous particularly if the chip mounting region is situated more deeply within the carrier than the region which surrounds it and which can contain, for example, the lead or other electrical contacts.
In another configuration, a carrier serving as a heat sink and having a planar chip mounting region is provided and a contact-connection layer is applied thereon. The carrier can be a PCB, a ceramic substrate, a metal core, a plastic or else a combination of these carrier materials.
Outside the chip mounting region, a dielectric layer is applied to the carrier in a planar fashion in order to avoid a short circuit with the chip mounting region. Conductor tracks and contact pads and also other necessary elements are then vapor-deposited, deposited or applied in some other way on the dielectric layer. The chip mounting region is furthermore correspondingly structured for the purpose of producing the first and/or second partial region and a solder material is subsequently deposited onto the at least one second partial region, for example by means of a solder dispensing method. As a result of the structuring of the planar chip mounting region, the solder is forced into the at least one second partial region and wets the latter. Afterward, different optoelectronic components can be placed on the solder in the at least one second partial region and be intimately connected to the chip mounting region by means of the solder being heated. In a last step, an electrical contact-connection for feeding electrical energy is performed.
The electrical contact-connection can be effected by means of wire bonding, for example, in which bonding wires are connected firstly to the optoelectronic luminous bodies and secondly to contact pads outside the chip mounting region.
In a further configuration of the invention, the chip mounting region is subdivided into different second partial regions, of which in each case two adjacent second partial regions are separated by a section of the first partial region. In this way, a plurality of optoelectronic luminous bodies can be fixed on the chip mounting region in regions that are easily separated spatially but are very closely spaced apart. By way of example, it is possible to arrange optoelectronic luminous bodies, embodied for emitting light having different wavelengths, on the chip mounting region in such a way that a desired overall luminous pattern arises. In particular mixed colors, for example the color white, can be realized by arranging different luminous bodies on the chip mounting region. In this case, by means of a suitably thin structuring of the first partial region between two partial regions it is possible to achieve a substantially uninterrupted joining-together of the different optoelectronic luminous bodies.